1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of fabricating the semiconductor device, and more particularly, to a semiconductor device having multiple built-in semiconductor devices stacked and a method of fabricating the semiconductor device.
2. Description of the Related Art
In recent years, there is a demand to downsize semiconductor devices used as non-volatile storage media for portable electronic devices such as portable phones and IC memory cards. It is particularly demanded to package semiconductor chips efficiently. One of the packaging techniques is to stack packages (built-in semiconductor devices) each having a semiconductor chip.
Referring to FIGS. 1 and 2, a description will now be given of a semiconductor device in accordance with a first related art, which is a built-in semiconductor device having a lower semiconductor device 29a and an upper semiconductor device 39, which devices are stacked. A semiconductor chip 20 is mounted on a wiring substrate 10 made of, for example, glass epoxy resin. Wires 22 electrically connect the semiconductor chip 20 and pads 15 provided on the wiring substrate 10. Solder balls 18a are provided on land electrodes 16 provided on a side of the wiring substrate 10 on which the semiconductor chip 20 is arranged. The semiconductor chip 20 is sealed with a resin seal portion 24a made of epoxy resin. The resin seal portion 24a is not provided to a region in which the solder balls 18a are arranged, but is provided in a central portion in which the semiconductor chip 20 is mounted. Solder balls 12 are provided on land electrodes 14 provided on another side of the wiring substrate 10 opposite to the side on which the semiconductor chip 20 is provided. Connection portions 17 electrically connect the land electrodes 16 and the solder balls 12. The solder balls 18a function as upper connection terminals for making connection with an upper semiconductor device. The semiconductor balls 12 function as lower connection terminals for making connections with a lower semiconductor device or a motherboard.
Referring to FIG. 2, the upper semiconductor device 39 has a wiring substrate 30 on which semiconductor chips 40 and 42 are stacked in this order. Wires 44 and 46 are used to electrically connect the semiconductor chips 40 and 42 and the wiring substrate 30. The semiconductor chips 40 and 42 are sealed with a resin seal portion 48. Since no built-in semiconductor device is provided on the top of the upper semiconductor device 39, no solder balls are provided on a side of the wiring substrate 30 on which the semiconductor chips 40 and 42 are provided. Thus, the resin seal portion 48 is provided on the whole upper surface of the wiring substrate 30. Land electrodes 34 are provided on another side of the wiring substrate 30 opposite to the side on which the semiconductor chips 40 and 42 are provided. The land electrodes 34 are connected to the solder balls 18a of the lower semiconductor device 29a. Thus, electrical connections are made between the upper semiconductor device 39 and the lower semiconductor device 29a. Connection portions for making connections between the wires 44 and 46 and the land electrodes 34 are not illustrated.
Japanese Patent Application Publication No. 2004-327855 (Document 1) discloses a semiconductor device in which the whole surface of a wiring substrate is sealed with a resin seal portion and upper connection terminals protrude from the resin seal portion.
The semiconductor device of the first related art does not have a high non-defective ratio because the lower semiconductor device 29a and the upper semiconductor device 39 in the stacked state have different degrees of thermal warping. In addition, the conventional semiconductor device has large financial and time burdens because it needs a metal mold for the resin seal portion 24 that matches in size with the semiconductor chip 20 of the lower semiconductor device 29a. Furthermore, the solder balls 18a are exposed and may be short-circuited due to a foreign particle or the like. It should be noted that the lower semiconductor device 29a and the upper semiconductor device 39 must be mutually positioned in order to connect these devices with the solder balls 18a. This positioning needs a specific tool, which will increase the manufacturing cost.